An incremental sigma-delta ADC is designed for column-parallel ADC array in CMOS image sensor. Sigma-delta modulator with single-loop single-bit structure is chosen for power consumption and performance reasons. Second-order modulator is used to reduce conversion time, without stability problem and large area accompanied by higher order sigma-delta modulator. The asymmetric current mirror amplifier used in integrator reduces more than 30% power dissipation. The digital filter and decimator are implemented by counters and adders with significantly reduced chip area and power consumption. A Clock generator is shared by 8 ADCs for trade-off among power, area and clock loading. The ADC array is implemented in a 0.18-μm CMOS technology and clocked at 10 MHz, and the simulated resolution achieves 15-bit with 255 clock cycles. The average power consumption per ADC is 118 μW including clock generator, and the area is only 0.0053 μm2.


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    Title :

    A 15-bit incremental sigma-delta ADC for CMOS image sensor


    Contributors:
    Chen, Nan (author) / Li, Zhengfen (author) / Zhong, Shengyou (author) / Zou, Mei (author) / Yao, Libin (author)

    Conference:

    Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II ; 2014 ; China,China


    Published in:

    Publication date :

    2015-04-13





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English