This paper describes the standard cell ASIC design methodology for a serial bus controller chip. This is a prototype CMOS chip which was designed in 19 weeks for an automotive application. The chip includes testability circuits which help attain 98% fault coverage.


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    Title :

    A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control


    Additional title:

    Sae Technical Papers


    Contributors:

    Conference:

    SAE Future Transportation Technology Conference and Exposition ; 1987



    Publication date :

    1987-08-01




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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