This paper describes the standard cell ASIC design methodology for a serial bus controller chip. This is a prototype CMOS chip which was designed in 19 weeks for an automotive application. The chip includes testability circuits which help attain 98% fault coverage.
A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control
Sae Technical Papers
SAE Future Transportation Technology Conference and Exposition ; 1987
1987-08-01
Aufsatz (Konferenz)
Englisch
A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control
Kraftfahrwesen | 1987
|Synthesis of Easily Testable AND-EXOR Networks
British Library Online Contents | 2011
|Fast turnaround expected for Seastar fast ferry
Online Contents | 2011
NEWS - Fast turnaround for Hercules Leader
Online Contents | 2004
SOLUTIONS - Computers-Electronics - Command Interface ASIC -- Analog Interface ASIC Chip Set
Online Contents | 2003