This paper describes the standard cell ASIC design methodology for a serial bus controller chip. This is a prototype CMOS chip which was designed in 19 weeks for an automotive application. The chip includes testability circuits which help attain 98% fault coverage.
A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control
Sae Technical Papers
SAE Future Transportation Technology Conference and Exposition ; 1987
01.08.1987
Aufsatz (Konferenz)
Englisch
A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control
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