Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.


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    Title :

    Estimating Delays In ASIC's


    Contributors:
    Burke, Gary (author) / Nesheiwat, Jeffrey (author) / Su, Ling (author)

    Published in:

    Publication date :

    1994-08-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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