Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.


    Zugriff

    Zugriff über TIB

    Verfügbarkeit in meiner Bibliothek prüfen


    Exportieren, teilen und zitieren



    Titel :

    Estimating Delays In ASIC's


    Beteiligte:
    Burke, Gary (Autor:in) / Nesheiwat, Jeffrey (Autor:in) / Su, Ling (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    1994-08-01



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch




    Predicting Lifetimes Of CMOS ASIC's From Test Data

    Buehler, Martin G. / Zamani, Nasser / Zoutendyk, John A. | NTRS | 1993


    Estimating Magnitude and Duration of Incident Delays

    Garib, A. / Radwan, A. E. / Al-Deek, H. | British Library Online Contents | 1997


    Estimating Signalized Intersection Delays to Transit Vehicles

    Hellinga, Bruce / Yang, Fei / Hart-Bishop, Jordan | Transportation Research Record | 2011