Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Cascaded VLSI Chips Help Neural Network To Learn


    Contributors:

    Published in:

    Publication date :

    1993-12-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English





    VLSI Neural Networks Help To Compress Video Signals

    Fang, Wai-Chi / Sheu, Bing J. | NTRS | 1996



    One-micron VLSI chips for military systems

    Eldon, J. / Gagnon, M. / Williams, F. | Tema Archive | 1983


    Integration of Intelligence for Robotics in VLSI Chips

    Kameyama, M. | British Library Online Contents | 1996