This paper describes the architecture of the Data Interface Facility, (DIF), a key element in NASA's advanced communications systems, and its core element, the Return Link Processor (RLP). Current activities to prototype some of the primary functions of the RLP are presented. It is shown how the prototype elements can be integrated into a full-performance DIF RLP.


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    Title :

    High speed VLSI systems for NASA's telemetry return link processor


    Contributors:

    Conference:

    ITC/USA/''89 ; 1989 ; San Diego, CA, United States


    Publication date :

    1989-01-01


    Type of media :

    Conference paper


    Type of material :

    No indication


    Language :

    English




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