This paper describes the architecture of the Data Interface Facility, (DIF), a key element in NASA's advanced communications systems, and its core element, the Return Link Processor (RLP). Current activities to prototype some of the primary functions of the RLP are presented. It is shown how the prototype elements can be integrated into a full-performance DIF RLP.


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    Titel :

    High speed VLSI systems for NASA's telemetry return link processor


    Beteiligte:

    Kongress:

    ITC/USA/''89 ; 1989 ; San Diego, CA, United States


    Erscheinungsdatum :

    01.01.1989


    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Keine Angabe


    Sprache :

    Englisch




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