Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.
Multiplier Architecture for Coding Circuits
NASA Tech Briefs ; 9 , 4
1986-03-01
Miscellaneous
No indication
English
Compact, Flexible Telemetry-Coding Circuits
NTRS | 1993
|A Compensation Method of Quantizing Error and Its Circuits Implementation for Fixed-Width Multiplier
British Library Online Contents | 2011
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