The architectural basis for an advanced fault tolerant on-board computer to succeed the current generation of fault tolerant computers is examined. The network error tolerant system architecture is studied with particular attention to intercluster configurations and communication protocols, and to refined reliability estimates. The diagnosis of faults, so that appropriate choices for reconfiguration can be made is discussed. The analysis relates particularly to the recognition of transient faults in a system with tasks at many levels of priority. The demand driven data-flow architecture, which appears to have possible application in fault tolerant systems is described and work investigating the feasibility of automatic generation of aircraft flight control programs from abstract specifications is reported.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Fault tolerant architectures for integrated aircraft electronics systems, task 2


    Contributors:

    Publication date :

    1984-06-01


    Type of media :

    Report


    Type of material :

    No indication


    Language :

    English




    Fault-tolerant and self-testable architectures for zero failure electronics

    Richardson, A. / Betts, W. R. / Institution of Electrical Engineers et al. | British Library Conference Proceedings | 1997


    Fault-tolerant and self-testable architectures for zero failure electronics

    Richardson,A. / Sharif,E. / Betts,W.R. et al. | Automotive engineering | 1997




    Fault-Tolerant Architectures With Enhanced Bus Protection for Electric/Hybrid Aircraft Systems

    Siddavatam, Anil Kumar Reddy / RajaShekara, Kaushik / Reddy, Ravi Prakash et al. | IEEE | 2023