A detailed description of the design approach and tradeoffs encountered during the development of the 50 MBPS decoder system is presented. A functional analysis of each of the major logical functions is given, and the system's major components are listed.


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    Title :

    High bit rate convolutional channel encoder/decoder


    Publication date :

    1977-06-20


    Type of media :

    Report


    Type of material :

    No indication


    Language :

    English





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