The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.


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    Title :

    Plated wire memory subsystem


    Contributors:

    Publication date :

    1974-02-01


    Type of media :

    Report


    Type of material :

    No indication


    Language :

    English


    Keywords :


    Plated wire memory subsystem

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