In this paper, a high speed pipelined architecture with pipeline scheduler is presented for the JPEG2000 arithmetic encoder. The new design has removed the need for the additional hardware units for the procedures of the encoding process with suitably controlling the pipeline stages. The proposed system is described in Verilog HDL and targeted for the Xilinx Virtex-5 FPGA family. Results of the timing analysis showed that designed architecture is able to achieve 132 Msymbols/sec throughput.
A high throughput MQ arithmetic encoder implementation for JPEG2000
2011-06-01
1148699 byte
Conference paper
Electronic Resource
English
Design of High Efficient JPEG2000 Bit-Plane Encoder
British Library Online Contents | 2005
|Design of New Pipeline Arithmetic Encoder
British Library Online Contents | 2004
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