Existing JPEG2000 2D-DWT architectures all fail to achieve a higher system throughput because they do not exploit the parallelisms fully. In this paper, a high throughput 2D-DWT encoding system is proposed firstly. It exploits three parallelisms of the 2D-DWT algorithm to achieve 1.7 times system throughput over the fastest existing design. For a one-level N × N 2D-DWT, it takes only N2/4 + N cycles. Because high throughput demands great bandwidth, an efficient memory subsystem is designed to support our high throughput 2D-DWT system. The on-chip memory requirement is only 11N. The proposed system is verified with software/hardware codesign technology based on the OpenJPEG software and a FPGA-based hardware platform.


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    Title :

    Efficient Memory Subsystem for High Throughput JPEG2000 2D-DWT Encoder


    Contributors:
    Li, Bao-Feng (author) / Dou, Yong (author) / Shao, Qiang (author)


    Publication date :

    2008-05-01


    Size :

    338461 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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