We propose a dual core JPEG2000 architecture which aims to compress high resolution multichannel images in real time. The proposed architecture handles both lossless and Rate Distortion-Optimized lossy compression schemes of JPEG2000. The dual core JPEG2000 architecture is implemented and simulated on a Xilinx Virtex-5 Series FPGA. The simulation results show that the proposed architecture can encode up to 200Mbits at 100MHz clock speed.


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    Title :

    A dual-core ASIC architecture for high-speed on-board image compression with JPEG2000


    Contributors:
    Ismailoglu, N. (author) / Karakus, K. (author) / Kapucu, K. (author) / Yilmaz, O. (author) / Mert, Y. M. (author) / Kazak, H. E. (author) / Oktem, R. (author)


    Publication date :

    2011-06-01


    Size :

    1175268 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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