We propose a dual core JPEG2000 architecture which aims to compress high resolution multichannel images in real time. The proposed architecture handles both lossless and Rate Distortion-Optimized lossy compression schemes of JPEG2000. The dual core JPEG2000 architecture is implemented and simulated on a Xilinx Virtex-5 Series FPGA. The simulation results show that the proposed architecture can encode up to 200Mbits at 100MHz clock speed.
A dual-core ASIC architecture for high-speed on-board image compression with JPEG2000
01.06.2011
1175268 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
JPIC - Rad-Hard JPEG2000 Image Compression ASIC
British Library Conference Proceedings | 2010
|Graphics Image Compression Using JPEG2000
IEEE | 2008
|Tuning JPEG2000 Image Compression for Graphics Regions
British Library Conference Proceedings | 2002
|Tuning JPEG2000 image compression for graphics regions
IEEE | 2002
|Image compression: Maxshift ROI encoding options in JPEG2000
British Library Online Contents | 2008
|