We propose a dual core JPEG2000 architecture which aims to compress high resolution multichannel images in real time. The proposed architecture handles both lossless and Rate Distortion-Optimized lossy compression schemes of JPEG2000. The dual core JPEG2000 architecture is implemented and simulated on a Xilinx Virtex-5 Series FPGA. The simulation results show that the proposed architecture can encode up to 200Mbits at 100MHz clock speed.


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    Titel :

    A dual-core ASIC architecture for high-speed on-board image compression with JPEG2000


    Beteiligte:
    Ismailoglu, N. (Autor:in) / Karakus, K. (Autor:in) / Kapucu, K. (Autor:in) / Yilmaz, O. (Autor:in) / Mert, Y. M. (Autor:in) / Kazak, H. E. (Autor:in) / Oktem, R. (Autor:in)


    Erscheinungsdatum :

    01.06.2011


    Format / Umfang :

    1175268 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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