This paper describes the development of a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. Several fixed-point number optimizations are described with emphasis on maximizing speed and/or minimizing FPGA area. Twiddle factor bit precision and its effects on FPGA area usage are also explored.
Automatic VHDL generation software tool for parameterized FPGA based FFT architectures
2010-07-01
1561865 byte
Conference paper
Electronic Resource
English
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