We have proposed and experimentally demonstrate high-speed clock recovery by employing a novel optoelectronic phase-locked loop. The DC ambiguity caused by the use of optoelectronic phase detector is resolved by balanced photodetection. Low timing jitter of the recovered clock indicates a potential for operation beyond 100 Gb/s using this scheme.


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    Title :

    High speed clock recovery using an optoelectronic phase locked loop implemented with balanced photodetection


    Contributors:
    Tong, D.T.K. (author) / Mikkelsen, B. (author) / Raybon, G. (author) / Nielsen, T.N. (author)


    Publication date :

    1999-01-01


    Size :

    161236 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English




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