We have proposed and experimentally demonstrate high-speed clock recovery by employing a novel optoelectronic phase-locked loop. The DC ambiguity caused by the use of optoelectronic phase detector is resolved by balanced photodetection. Low timing jitter of the recovered clock indicates a potential for operation beyond 100 Gb/s using this scheme.


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    Titel :

    High speed clock recovery using an optoelectronic phase locked loop implemented with balanced photodetection


    Beteiligte:
    Tong, D.T.K. (Autor:in) / Mikkelsen, B. (Autor:in) / Raybon, G. (Autor:in) / Nielsen, T.N. (Autor:in)


    Erscheinungsdatum :

    01.01.1999


    Format / Umfang :

    161236 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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