SH-Navi3 embeds ■ High performance dual RISC processors (1920 MIPS) ■ 2D/3D graphic accelerators ■ Image recognition engine — High-speed processing (up to 53.3GOPS): parallel processing + pipeline architecture + function specific accelerator — Bus traffic reduction & Line programmability: PIPE architecture
SoC for car navigation systems with a 53.3 GOPS image recognition engine
2009-08-01
13901552 byte
Conference paper
Electronic Resource
English
A 100 GOPS vision platform for intelligent vehicles
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