A new and efficient design of a 4 /spl times/ 4 array of single bit optical reduced instruction set computer (RISC) processors demonstrating data distribution through an integrated CMOS photodetector and photoreceiver alleviating bandwidth and interconnect delay limitations is presented. The proposed chip monolithically integrates optical sensors with CMOS based logic circuits with a RISC to create a generically programmable smart pixel.


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    Title :

    Configurable architecture for smart pixel research


    Contributors:


    Publication date :

    2002-01-01


    Size :

    150608 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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