A new and efficient design of a 4 /spl times/ 4 array of single bit optical reduced instruction set computer (RISC) processors demonstrating data distribution through an integrated CMOS photodetector and photoreceiver alleviating bandwidth and interconnect delay limitations is presented. The proposed chip monolithically integrates optical sensors with CMOS based logic circuits with a RISC to create a generically programmable smart pixel.


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    Titel :

    Configurable architecture for smart pixel research


    Beteiligte:
    Raman, K.S. (Autor:in) / Chokhani, A. (Autor:in) / Vagheeswar, V.S. (Autor:in) / Beyette, F.R. (Autor:in)


    Erscheinungsdatum :

    01.01.2002


    Format / Umfang :

    150608 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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