A new and efficient design of a 4 /spl times/ 4 array of single bit optical reduced instruction set computer (RISC) processors demonstrating data distribution through an integrated CMOS photodetector and photoreceiver alleviating bandwidth and interconnect delay limitations is presented. The proposed chip monolithically integrates optical sensors with CMOS based logic circuits with a RISC to create a generically programmable smart pixel.
Configurable architecture for smart pixel research
The 15th Annual Meeting of the IEEE Lasers and Electro-Optics Society ; 2 ; 905-906 vol.2
01.01.2002
150608 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
ThDD5 Configurable Architecture for Smart Pixel Research
British Library Conference Proceedings | 2002
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British Library Conference Proceedings | 2001
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