The combination of two synergistic VLSI technologies, ultra low power CMOS and radiation tolerant by design, offers an opportunity to provide advanced electronics capabilities for future spacecraft. The 500 mV CMOS process can yield orders of magnitude power reduction compared to current space-flight technologies and the radiation tolerance provides immunity against single event latch-up, good single event upset resistance and total ionizing dose immunity of at least 200 krads(Si). A study based on the EO-1 spacecraft requirements indicates that the use of these technologies could provide spacecraft power savings of 73% and total mass savings of 16%.


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    Title :

    Low power radiation tolerant VLSI for advanced spacecraft


    Contributors:
    Benz, H.F. (author) / Gambles, J.W. (author) / Whitaker, S.R. (author) / Hass, K.J. (author) / Maki, G.K. (author) / Pen-Shu Yeh, (author)


    Publication date :

    2002-01-01


    Size :

    389745 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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