In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)/sup 2/ 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is T/sub AND/ + [log/sub 2/(m + 1)]T/sub XOR/. The proposed architectures are highly modular and well suited for high speed VLSI implementations.
Efficient parallel finite field modular multiplier
2003-01-01
201738 byte
Conference paper
Electronic Resource
English
Effcient Parallel Finite Field Modular Multiplier
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