This paper will discuss a packet switch demonstrator, which is being implemented on separate programmable logic devices forming electronic "islands" interconnected by a reconfigurable central stage crossbar with the capability of emulating optical link delay. The current design will have 8 inputs and 8 outputs and each sector will be a 4/spl times/4 sub-switch implemented on a single field-programmable gate array (FPGA) with shared buffer memory. Communication among modules within the demonstrator is performed through a custom high speed 10Mbps interface.


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    Title :

    Packet switch using reconfigurable optical central crossbars


    Contributors:
    Abdo, A. (author) / Bishtein, V. (author) / Dicorato, P.G. (author) / Paredes, S.A. (author) / Hall, T.J. (author)


    Publication date :

    2005-01-01


    Size :

    251080 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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