Presents a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. The authors show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. The design of the 8/spl times/8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2/spl mu/ CMOS technology.<>


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    Title :

    Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip


    Contributors:


    Publication date :

    1994-01-01


    Size :

    484595 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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