Presents a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. The authors show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. The design of the 8/spl times/8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2/spl mu/ CMOS technology.<>
Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip
Proceedings of 1st International Conference on Image Processing ; 3 ; 606-610 vol.3
01.01.1994
484595 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip
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