Presents a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. The authors show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. The design of the 8/spl times/8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2/spl mu/ CMOS technology.<>


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip


    Beteiligte:


    Erscheinungsdatum :

    01.01.1994


    Format / Umfang :

    484595 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip

    Srinivasan, V. / Liu, K. J. R. / IEEE; Signal Processing Society | British Library Conference Proceedings | 1994


    ICX:A custom VLSI-chip for engine control

    Geering,H.P. / ETH Zuerich,CH | Kraftfahrwesen | 1989


    ICX: A custom VLSI-chip for engine control

    Geering, H.P. | Tema Archiv | 1989


    ICX, a custom VLSI-chip for engine control

    Geering,H.P. / ETH Zuerich,CH | Kraftfahrwesen | 1989


    High throughput 2d Dct/Idct Processor for Video Coding

    Ruiz, G. A. / Michell, J. A. / Buron, A. M. | British Library Conference Proceedings | 2005