In this paper, we present an automatic soft IP (Intellectual Property) generation method for high-speed Viterbi decoders. In our scheme, the synthesizable HDL (Hardware Description Language) code for the Viterbi decoder is automatically produced depending on not only the system parameters such as a coding rate but also the hardware architecture for parallel processing. The proposed method is implemented by using C++ language, and the HDL codes automatical-ly generated by the computer program are verified by using an HDL simulator and synthesized into gate-level circuits with 0.13um CMOS library. From the results, we can find that the proposed method can be a good solution to reduce the time required for hardware design of Viterbi decoder considerably because our scheme can prevent from potential human errors effectively in the HDL code design process.
Design and Implementation of a Soft IP Generator for High-Speed Viterbi Decoders
2008 Congress on Image and Signal Processing ; 2 ; 568-572
2008-05-01
1007395 byte
Conference paper
Electronic Resource
English
Viterbi Decoders Generation for FPGA Platforms
IEEE | 2013
|Joint Synchronization of Viterbi and Reed-Solomon Decoders
Online Contents | 1995
The Application of Smart Pixels to High Performance Viterbi Decoders
British Library Conference Proceedings | 1994
|Soft-output Viterbi decoding:VLSI implementation issues
Automotive engineering | 1993
|