In this paper, we present an automatic soft IP (Intellectual Property) generation method for high-speed Viterbi decoders. In our scheme, the synthesizable HDL (Hardware Description Language) code for the Viterbi decoder is automatically produced depending on not only the system parameters such as a coding rate but also the hardware architecture for parallel processing. The proposed method is implemented by using C++ language, and the HDL codes automatical-ly generated by the computer program are verified by using an HDL simulator and synthesized into gate-level circuits with 0.13um CMOS library. From the results, we can find that the proposed method can be a good solution to reduce the time required for hardware design of Viterbi decoder considerably because our scheme can prevent from potential human errors effectively in the HDL code design process.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Design and Implementation of a Soft IP Generator for High-Speed Viterbi Decoders


    Contributors:


    Publication date :

    2008-05-01


    Size :

    1007395 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    Viterbi Decoders Generation for FPGA Platforms

    Espinosa, Luis Alberto Luna / Sanchez, Juan de Dios Lopez / Hipolito, Juan Ivan Nieto et al. | IEEE | 2013


    Joint Synchronization Of Viterbi And Reed-Solomon Decoders

    Statman, Joseph I. / Chauvin, Todd H. / Cheung, Kar-Ming et al. | NTRS | 1995



    The Application of Smart Pixels to High Performance Viterbi Decoders

    IEEE; Lasers and Electro-Optics Society | British Library Conference Proceedings | 1994


    Soft-output Viterbi decoding:VLSI implementation issues

    Joeressen,O.J. / Vaupel,M. / Meyr,H. et al. | Automotive engineering | 1993