A real-time architecture was designed, developed and fabricated that targets an application through the MiP (Monolithic Interceptor Processor) program. This MCM, as an elemental building block for parallel real-time DSP applications was designed and built in the standard MiP size and format. This PDA (Parallel Digital signal processing Array) is capable of 400 MFLOPS (at 33 MHz) within a volume of 2 in/sup 3/. Due to the minimized circuit parasitics of HDI packaging, much higher clock speed, hence MFLOPS, are quite likely. Though the evaluation of the PDA was not completed, the MiP project developed what could be the smallest and most capable real-time PDA to date. In order to support intermediate testing, a key "known good module" test fixture was also developed. It then provided for the demonstration of key design and methodologies that continue to be used.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Design and fabrication of a tri-C30 multichip module building block


    Contributors:
    Staggs, J. (author) / Smith, J. (author)


    Publication date :

    1997-01-01


    Size :

    566859 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    Design and Fabrication of a Tri-C30 Multichip Module Building Block

    Staggs, J. / Smith, J. / IEEE et al. | British Library Conference Proceedings | 1997


    Design and fabrication of optoelectronic multichip module prototypes using MEMS fabrication techniques [3008-05]

    Koh, S. / Sadler, D. J. / Oh, K. et al. | British Library Conference Proceedings | 1997



    Tunneling Accelerometer Multichip Module

    Boyadzhyan, V. V. / Choma, J., Jr. | NTRS | 1998


    Military multichip module packaging design and manufacture

    Cleveland, C. / Pietila, D. / Rassaian, M. et al. | Tema Archive | 1992