The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the proposed technique. Finally, simulation results are presented to verify the effectiveness of the proposed scheme.<>


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    Title :

    Multiprocessor design using joint transform correlator


    Contributors:
    Alam, M.S. (author)


    Publication date :

    1993-01-01


    Size :

    458935 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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