Academic Predictable Multi-core Processor: MERASA & PRET processors COTS architecture: IBM™ Cell, Freescale™'s MPC8641D & QorIQ Platform Local memories (scratchpads & caches): • Best cache policy (for analyzability) • Cache Analysis (optimization to reduce cache pollution) • Shared Cache Strategy to reduce interferences Interconnect Element: • Shared Bus (bounding access time) • Ring protocols • CoreNet, & Data Path Accelerator Architecture


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    Title :

    A design approach for predictable and efficient multi-core processor for avionics


    Contributors:


    Publication date :

    2011-10-01


    Size :

    7542499 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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