Academic Predictable Multi-core Processor: MERASA & PRET processors COTS architecture: IBM™ Cell, Freescale™'s MPC8641D & QorIQ Platform Local memories (scratchpads & caches): • Best cache policy (for analyzability) • Cache Analysis (optimization to reduce cache pollution) • Shared Cache Strategy to reduce interferences Interconnect Element: • Shared Bus (bounding access time) • Ring protocols • CoreNet, & Data Path Accelerator Architecture


    Zugriff

    Download


    Exportieren, teilen und zitieren



    Titel :

    A design approach for predictable and efficient multi-core processor for avionics


    Beteiligte:
    Agrou, Hicham (Autor:in) / Gatti, Marc (Autor:in) / Sainrat, Pascal (Autor:in) / Toillon, Patrice (Autor:in)


    Erscheinungsdatum :

    01.10.2011


    Format / Umfang :

    7542499 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    A design approach for predictable and efficient multi-core processor for avionics

    Agrou, Hicham / Sainrat, Pascal / Gatti, Marc et al. | IEEE | 2011


    Introduction to advanced avionics core processor

    Yuanzhi, C. / Shiyi, M. | British Library Online Contents | 1997


    Distributed processor design for avionics

    Moore, M.J. | Tema Archiv | 1975


    Realtime avionics processor emulators

    Finley, R.W. / Pflasterer, C.A. | IEEE | 1993


    Digital avionics display processor

    HAMILTON, JR., E. / PETROFSKY, S. | AIAA | 1981