For space applications, high performance and high reliability are two indicators that become more and more important to a processor. After an analysis of the different architectures and fault tolerant techniques, an implementation of CORDIC processor employing 3N codes for error detection in a 3 granularly pipelined architecture is presented. A high data throughput of 300MFLOPS is achieved and the circuit complexity only increased 9.5% after applied the fault tolerant technique.


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    Title :

    High-performance fault-tolerant CORDIC processor for space applications


    Contributors:
    Sicong Wang, (author) / Zhiping Wen, (author) / Lixin Yu, (author)


    Publication date :

    2006-01-01


    Size :

    3647434 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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