For space applications, high performance and high reliability are two indicators that become more and more important to a processor. After an analysis of the different architectures and fault tolerant techniques, an implementation of CORDIC processor employing 3N codes for error detection in a 3 granularly pipelined architecture is presented. A high data throughput of 300MFLOPS is achieved and the circuit complexity only increased 9.5% after applied the fault tolerant technique.
High-performance fault-tolerant CORDIC processor for space applications
2006-01-01
3647434 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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