In this paper we compare nine simulation alternatives which can be used for modeling and analysis the hardware components and processing tasks involved in processing a packet flow entering in a network node. In particular, we focus on the capabilities of these alternatives that can be employed for validating an analytical model based on Real-Time Calculus for the performance evaluation of the NIC's buffer requirements at high-level abstraction.


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    Title :

    Comparing Simulation Alternatives for High-Level Abstraction Modeling of NIC's Buffer Requirements in a Network Node


    Contributors:
    Garay, G R (author) / León, M (author) / Aguilar, R (author) / Alarcón, V (author)


    Publication date :

    2010-09-01


    Size :

    571264 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English




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