In this paper we compare nine simulation alternatives which can be used for modeling and analysis the hardware components and processing tasks involved in processing a packet flow entering in a network node. In particular, we focus on the capabilities of these alternatives that can be employed for validating an analytical model based on Real-Time Calculus for the performance evaluation of the NIC's buffer requirements at high-level abstraction.
Comparing Simulation Alternatives for High-Level Abstraction Modeling of NIC's Buffer Requirements in a Network Node
2010-09-01
571264 byte
Conference paper
Electronic Resource
English
British Library Conference Proceedings | 2008
|UAS behavior modeling based on high level abstraction
IEEE | 2011
|