In this paper we compare nine simulation alternatives which can be used for modeling and analysis the hardware components and processing tasks involved in processing a packet flow entering in a network node. In particular, we focus on the capabilities of these alternatives that can be employed for validating an analytical model based on Real-Time Calculus for the performance evaluation of the NIC's buffer requirements at high-level abstraction.


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    Titel :

    Comparing Simulation Alternatives for High-Level Abstraction Modeling of NIC's Buffer Requirements in a Network Node


    Beteiligte:
    Garay, G R (Autor:in) / León, M (Autor:in) / Aguilar, R (Autor:in) / Alarcón, V (Autor:in)


    Erscheinungsdatum :

    01.09.2010


    Format / Umfang :

    571264 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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