Using Dynamic Partial Reconfiguration (DPR) of FPGAs, several circuits can be time-multiplexed on the same chip region, saving considerable area. However, the long reconfiguration time when switching between circuits remains a large problem with DPR. In this paper we show it is possible to significantly reduce reconfiguration time when the number of circuits is limited. We tackle the problem by reducing the time needed to reconfigure the FPGA's routing. We divide the configuration memory of the FPGA's routing in a static and a dynamic portion. A novel router, called StaticRoute, is presented that is able to route the nets of the different circuits in such a way that the static portion is shared and only the dynamic portion needs to be reconfigured. The static portion of the configuration memory does not need to be rewritten during run-time. In the experiments we show it is possible to reach a 2× speed-up of the reconfiguration process, while the increase in wire length per circuit is limited.


    Access

    Download


    Export, share and cite



    Title :

    StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs



    Publication date :

    2013-01-01


    Remarks:

    International Conference on Field Programmable and Logic Applications ; ISSN: 1946-1488 ; ISBN: 9781479900046



    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    Classification :

    DDC:    629



    Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

    Tambara, Lucas A. / Tarrillo, Jimmy / Kastensmidt, Fernanda L. et al. | Springer Verlag | 2016



    Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS

    DI CARLO, STEFANO / GAMBARDELLA, GIULIO / INDACO, MARCO et al. | BASE | 2013

    Free access

    Dynamic Partial Reconfiguration Through Ethernet Link

    Llamocca, D. / Pattichis, M. / Vera, A. et al. | British Library Conference Proceedings | 2010


    Dynamic Partial Reconfiguration Through Ethernet Link

    Llamocca, Daniel / Pattichis, Marios / Vera, Alonzo et al. | AIAA | 2010