Content Addressable Memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and sense amplifiers are highly sought-after in CAM In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. We propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.A CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it.
A High Speed Low Power Cam And Tcam With A Parity Bit And Power Gated Ml Sensing
2014-02-25
Article (Journal)
Electronic Resource
English
CAM , Amplifiers , Loop , Architectures
DDC: | 629 |
Research on TCAM Match Algorithm in High-Speed DPI System
British Library Conference Proceedings | 2012
|Development of the urban traffic control system for London-TCAM
Tema Archive | 2000
|Development of the Urban Traffic Control System for London - TCAM
British Library Conference Proceedings | 2000
|The next generation UTC data transmission system for London -TCAM
British Library Conference Proceedings | 1998
|High Power Density High Speed Diesel
Online Contents | 2016
|