Content Addressable Memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and sense amplifiers are highly sought-after in CAM In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. We propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.A CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it.


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    Titel :

    A High Speed Low Power Cam And Tcam With A Parity Bit And Power Gated Ml Sensing


    Beteiligte:

    Erscheinungsdatum :

    2014-02-25


    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Klassifikation :

    DDC:    629



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