Access

    Access via TIB

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    CMOS VLSI Implementation of a Digital Logarithmic Multiplier



    Conference:

    National aerospace and electronics conference ; 1996 ; Dayton; OH



    Publication date :

    1996-01-01


    Size :

    4 pages


    Remarks:

    Also known as NAECON 1996. IEEE Cat nos 96CH35934 and 96CB35934




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




    Multiplier-less Digital Down Converter in 90nm CMOS technology

    Ren, Saiyu / Billman, Steven / Siferd, Ray | IEEE | 2011


    Optimization of Digital Filter Structures for VLSI Implementation

    Saromaeki, T. / Ritoniemi, T. | British Library Online Contents | 1993


    A VLSI Macrocell Implementation for Digital Neural Nets

    Fornaciari, W. / Salice, F. / IEEE et al. | British Library Conference Proceedings | 1994


    Pulse Width Amplitude Modulation Based CMOS Multiplier

    Astro, R / Gómez, H / Salinas, J et al. | IEEE | 2010


    Unique applications of advanced VLSI CMOS

    SENDZUK, G. / SPAANENBURG, H. | AIAA | 1983