Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Modular VLSI Reed-Solomon Decoder
NASA Tech Briefs ; 15 , 9
1991-09-01
Sonstige
Keine Angabe
Englisch
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