Theoretical study takes new look at current-vs.-voltage behavior of silicon controlled rectifiers (SCR's), four-layer complementary metal oxide/semiconductor (CMOS) devices, and similar devices susceptible to latchup. For purposes of analysis, "latchup" denotes transition of such device from lower-current-conducting steady state to distinct higher-current-conducting steady state. Focuses upon conventional two-couple-transistor model of one-dimensional SCR. Although model gives oversimplified view of latchup in CMOS circuits, useful for qualitative predictions of electrical characteristics.


    Zugriff

    Zugriff über TIB

    Verfügbarkeit in meiner Bibliothek prüfen


    Exportieren, teilen und zitieren



    Titel :

    Relationship Between Latchup And Transistor Current Gain


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    01.08.1989



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch




    Latchup in CMOS Integrated Circuits

    Soliman, K. A. / Nichols, D. K. | NTRS | 1985


    Latent damage from single-event latchup

    Becker, H. N. / Miyahira, T. F. / Johnston, A. H. | NTRS | 2002


    Single Event Latchup Protection of Integrated Circuits

    Layton, P. / Marshall, J. / Czajkowski, D. et al. | British Library Conference Proceedings | 1997


    Single Event Latchup Protection of Integrated Circuits

    Layton, P. / Marshall, J. / Czajkowski, D. et al. | British Library Online Contents | 1997


    Latchup Test Consideration for Analog-to-Digital Converter

    Johnston, A. / Miyahira, T. | NTRS | 2000