Effects of the spacer-drain overlap on the performance parameters of the double gate tunnel field effect transistor is proposed and investigated in this paper. By proper fabrication of the spacer-drain overlap, we can obtain a lower sub-threshold swing, smaller short channel effect (SCEs), i.e. drain induced barrier lowering (DIBL), higher ON-state current (ION) and considerably less OFF-state current (IOFF). Here we also measure effects of the channel length variation of the device. In this paper, we compare the proposed device with single gate tunnel FET with spacer-drain overlap using vertical tunneling concept. So we can observed, that the proposed device gives better performance parameters.
TCAD simulations of double gate tunnel field effect transistor with spacer drain overlap base on vertical Tunneling
2017-04-01
358334 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
Porous-Floating-Gate Field-Effect Transistor
NTRS | 1990
|Flexible graphene field effect transistor with ferroelectric polymer gate
British Library Online Contents | 2016
|