Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
Porous-Floating-Gate Field-Effect Transistor
NASA Tech Briefs ; 14 , 7
1990-07-01
Sonstige
Keine Angabe
Englisch
Flexible graphene field effect transistor with ferroelectric polymer gate
British Library Online Contents | 2016
|Floating-Emitter Solar-Cell Transistor
NTRS | 1986
|British Library Online Contents | 1996
|JANTX2N4856 field-effect transistor
NTRS | 1980