This study presents a refined 16x16 Dadda multiplier optimized for parallel processing applications, integrating the Kung-Brent adder to enhance performance. By combining the Dadda multiplier’s efficient partial product reduction with the Kung-Brent adder’s reduced delay and area overhead, the design achieves notable improvements in power efficiency and speed. The use of parallel processing at multiple stages further accelerates computation, ensuring high throughput and low latency. Our thorough simulation and synthesis results demonstrate that this optimized multiplier surpasses traditional designs in key performance indicators, including speed, area, and efficiency. The enhanced design is particularly effective for high-demand parallel processing tasks and offers significant advancements in digital circuit design. This development not only provides a robust solution for efficient arithmetic operations but also paves the way for future innovations in digital multiplier technologies.
Enhanced 16 × 16 Dadda Multiplier Using Kung-Brent Adder for Superior Parallel Processing Performance
06.11.2024
1070139 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method
BASE | 2018
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