This chapter discusses intelligent fault‐tolerance techniques such as evolvable hardware fault‐tolerance techniques and artificial immune hardware fault‐tolerance techniques. These latest techniques can provide references for the fault‐tolerance design of next‐generation onboard computers. With the evolvable hardware fault‐tolerance technique, hardware fault‐tolerance is realized in accordance with evolution theory, and this came to prominence in the 1990s. The chapter also discusses the research conducted into modeling of evolution systems and summarizes various evolution methods fit for different programmable devices and architectures. In artificial immune hardware fault‐tolerance, the immunity concept is abstracted and applied in hardware system fault‐tolerance to enable hardware to possess features such as self‐study, self‐adaptation, and self‐recovery. Fault‐tolerance methods with artificial immune system are realized with FPGA. SRAM‐based FPGA is the mainstream FPGA development direction. Its high logic density and unlimited reprogrammable capability results in SRAM‐based FPGA being extensively used in various situations, and it is also the major focus of FPGA fault‐tolerance research.
Intelligent Fault‐Tolerance Techniques
2017-03-15
76 pages
Article/Chapter (Book)
Electronic Resource
English
Software Fault‐Tolerance Techniques
Wiley | 2017
|Fault‐Tolerance Techniques for FPGA
Wiley | 2017
|Three-Layer MPI Fault-Tolerance Techniques
IEEE | 2013
|Fault‐Tolerance Architectures and Key Techniques
Wiley | 2017
|Fault Tolerance Techniques Applied in ISO-AOCS
British Library Conference Proceedings | 1994
|