The requirements for space-based integrated circuit applications are defined with an emphasis on being radiation tolerant and low power consuming. Flexible analog signal processors (FASPs) are outlined as a means by which effective circuit designs can be utilized to perform a multitude of tasks. The development of complementary III-V technologies have been proven to meet the demands of the space environment, and have demonstrated the potential for frequency operation beyond 1 GHz using power supply voltages at or below 1.5 Volts. The novel fabrication process known as chi s-MET (pronounced kismet, which uses the Greek letter chi , and stands for complementary heterostructure integrated single metal transistor), is introduced as manufacturing technique to be used in FASP design. The chi s-MET fabrication process is outlined with preliminary device results presented. An example of a FASP circuit design using chi s-MET is provided. Conclusions regarding the utilization of the chi s-MET process for FASPs are outlined with comments focusing on a space-based demonstration.


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    Title :

    Xs-MET, a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications


    Contributors:
    Cerny, C. (author) / Via, D. (author) / Ebel, J. (author) / DeSaivo, G. (author) / Quach, T. (author) / Bozada, C. (author) / Dettmer, R. (author) / Gillespie, J. (author) / Jenkins, T. (author) / Pettiford, C. (author)


    Publication date :

    1997


    Size :

    8 Seiten, 15 Quellen




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English