A new approach to the design of microprocessor-based failsafe systems for railways that was used to design the FIRM architecture is described. The approach involves assigning appropriate levels of safety to system functions, depending on how critical they are, instead of using the same safety standard for all functions. The FIRM (short for failsafe interlocking system for railways using microprocessors) architecture uses a pair of processors that operate in a see-saw mode, with one or more pairs kept on standby. The installation and testing of an engineering prototype of the architecture that was fabricated for Indian Railways are discussed.


    Access

    Access via TIB

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    A fail-safe interlocking system for railways


    Additional title:

    Ein ausfallsicheres Kopplungssystem für Eisenbahnen


    Contributors:
    Chandra, V. (author) / Verma, M.R. (author)

    Published in:

    Publication date :

    1991


    Size :

    9 Seiten, 9 Quellen




    Type of media :

    Article (Journal)


    Type of material :

    Print


    Language :

    English




    An embedded fail-safe interlocking system

    Bin Pei / Ming, Yinghua | Tema Archive | 1997



    Relay interlocking on swiss federal railways

    Engineering Index Backfile | 1956


    FAIL-SAFE SYSTEM

    ITO HIROAKI | European Patent Office | 2021

    Free access

    Changing the Absolutist Safety Culture: Accepting that the Railways are not Fail Safe

    Godfrey, P. / AIC Conference Ltd | British Library Conference Proceedings | 1996