This report analyzes the feasibility of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessor. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (space) qualification schedule, and performance. The advantages of the i486 over the 386 are lower power consumption and higher floating-point performance in speed. The i486 on-chip cache, however, has neither parity check nor error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance in speed than the 386 without cache, which is the current DMS design choice. The benchmark performance of a 386-based prototype Flight Equivalent Unit (FEU), which is the closet configuration to the DMS design as of April 1991, is only about 50 % of a PS/2 Model 70 with cache, which is generally considered as a 4 MIPS (million instructions per second) computer. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial way to enhance computation-intensive performance for the current DMS design at this time.


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    Title :

    Analysis of the Intel 386 and i486 microprocessors for the space station Freedom data management system


    Additional title:

    Analyse der Mikroprozessoren Intel 386 und i486 für das Datenverwaltungssystem der Raumstation Freedom


    Contributors:


    Publication date :

    1991


    Size :

    10 Seiten, 4 Bilder, 10 Tabellen, 7 Quellen


    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English