A miniaturized, low-power parallel processor for space applications is under development by Space Computer Corporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size and power consumption for space-based sensor systems. Our approach for achieving this goal is to use low-power VLSI devices which maximize throughput per watt, together with three-dimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a 12-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches.


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    Title :

    Miniaturized, low-power parallel processor for space applications


    Additional title:

    Miniaturisierter Parallelprozessor mit geringer Leistungsaufnahme für die Raumfahrt


    Contributors:


    Publication date :

    1991


    Size :

    9 Seiten, 5 Bilder, 7 Quellen



    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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